1. Field of the Invention
The present invention relates to the design of semiconductor chips. More specifically, the present invention relates to a method and an apparatus for generating a model for a circuit cell timing analysis and for signal intengrity analysis.
2. Related Art
Timing and signal integrity are ever increasingly important issues in integrated circuit design in the deep submicron regime. One major challenge in timing and signal integrity analysis of such deep submicron VLSI chips is to accurately model effects like interconnect crosstalk noise. Crosstalk is generally caused by capacitive or inductive coupling of adjacent conductors, which results in a distortion in the voltage waveform. Such a distortion in an input signal of a circuit cell may result in incorrect logic transitions, e.g., a gate may switch at an incorrect time, or delay variations on a signal line. The delay variation may propagate downstream and cause timing violations in other parts of the design.
For crosstalk noise analysis, conventionally table lookup based approaches are used to model noise bump propagation through a circuit cell. The propagated noises are pre-characterized at given input noise height, width, and cell load capacitance values. Detailed description on noise propagation table based methods can be found in A. Gyure, A. Kasnavi, S. Lo, P. Tehrani, W. Shu, M. Shahram, J. Wang, and J. Zejda, “Noise Library Characterization for Large Capacity Static Noise Analysis Tools,” ISQED, pp. 28-34, 2005, which are incorporated herein. While being efficient in runtime, a drawback of the table lookup approach is that it requires long characterization time as well as large memory storage to accommodate the dense multi-dimensional tables that are often necessary to obtain relatively high accuracy.
Moreover, the accuracy of table lookup based approaches is not always adequate. For example, often the table lookup approaches may not explicitly model the effect of time to peak. When the time to peak is modeled, it requires an additional dimension in the lookup table, at a significant cost in storage and characterization time and still does not completely model the input noise waveform to a cell. Additionally, the table lookup approach typically uses an effective load capacitance to model cell load, which is another source of potential inaccuracy, as the effective capacitance value for crosstalk noise is often different from the effective capacitance for crosstalk delay. Even if the correct effective load capacitance value is used, a single capacitive load based table may still not be able to accurately represent the real load condition at the cell output node.
Further, table lookup based approaches are suitable only for noise propagation. Table lookup approaches are not suitable for problems such as driver weakening and the combination of propagated noise and injected noises. Detailed description on the noise combination problem can be found in, for example, V. Zolotov, D. Blaauw, S. Sirichotiyakul, M. Becer, C. Oh, R. Panda, A. Grinshpon, and R. Levy, “Noise Propagation and Failure Criteria for VLSI Designs,” ICCAD, pp. 587-594, 2002, which is incorporated herein.
Alternatively, waveform propagation through circuit cells can be handled by abstracting the circuit cells using a current model. FIG. 1 illustrates a time indexed current model 10 that is conventionally used for delay calculation where the input waveform to the circuit cell is a monotonically rising or falling waveform. The current model 10 uses a current source 12 and is pre-characterized at given input slew and output load capacitance values. The currents through the output load capacitance at an array of time indexes are stored in a table, which will be used later in a simulator to derive cell output waveform. The currents are therefore modeled as a function of the following three parameters input slew, output capacitance, and time, which is described, e.g., in US patent application 2005/0039151, which is incorporated herein. Using this method to model noise waveform propagation, it is necessary to pre-characterize the current source at given input noise height, width, and load capacitance values resulting to a four-dimensional table, which becomes prohibitively expensive in storage and characterization time.
Therefore, a different modeling approach for circuit cells is needed. FIG. 2 illustrates another current model 50, which is based on input voltage and output voltage of a cell. The current model 50 uses a Vin-Vout indexed lookup table for current source 52, an output terminal capacitance Cout, an optional Miller capacitance CM, and a time shift parameter Dt, which is used for better curve fitting. For signal integrity analysis, a low pass filter 54 with a delay constant τ is also included at the input side of the cell under study. It is noted that the time shifting of the output waveform is purely empirical. Although current model 50 works for crosstalk delay calculation, it does not provide adequate accuracy for noise propagation and driver weakening effects. Current model 50 is described in more detail in J. F. Croix and D. F. Wong, “Blade and Razor: Cell and Interconnect Delay Analysis Using Current-Based Models,” DAC, pp. 386-389, 2003, which is incorporated herein by reference. Another similar Vin-Vout indexed lookup table based current model is described in I. Keller, K. Tseng, and N. Verghese, “A Robust Cell-Level Crosstalk Delay Change Analysis,” ICCAD, pp. 147-154, 2004, which is also incorporated herein by reference.
Accordingly, improved cell level modeling that is suitable for various types of signal integrity analysis is desirable.